As illustrated in example FIG. 1A, a semiconductor device can include doping profile 10 in a poly-gate after ion implantation. As illustrated in example FIG. 1B, gate depletion is illustrated due to a poly-capacitance. As illustrated in example FIG. 1C, a graph illustrates voltage-capacitance characteristics of a transistor.
Currently, when a semiconductor substrate having a poly-gate formed thereon and/or thereover is subjected to ion implantation to produce a source/drain region, ions are implanted into the poly-gate as well as the semiconductor substrate, thereby forming a poly-resistor and a transistor. There is a high demand for high integration of semiconductor devices. Therefore, as can be appreciated from doping profile 10 illustrated in example FIG. 1A, due to a difference in the density of dopants in a poly-gate, a transistor gate, as illustrated in example FIG. 1B, may exhibit parasitic capacitance or poly-capacitance 14, causing gate depletion. The gate depletion can be clearly seen from a characteristic curve of capacitance C and voltage V as illustrated in example FIG. 1C. Consequently, the resulting transistor has an RC time-constant delay and a difficulty in the control of matching conditions with analogue devices. This makes it difficult to predict device performance and causes problems in circuit design.